BUFGMUX
BUFGMUX_GCLKMUX
- DISABLE_ATTR=[LOW:1]
- S=[S_INV:1] [S:0]
IBUF_PAD
IOB
IOB_OUTBUF
IOB_PAD
- DRIVEATTRBOX=[2:34] [12:2]
- IOATTRBOX=[LVCMOS33:36]
- SLEW=[SLOW:34] [FAST:2]
MULT18X18SIO
- CEA=[CEA_INV:0] [CEA:3]
- CEB=[CEB_INV:0] [CEB:3]
- CEP=[CEP:3] [CEP_INV:0]
- CLK=[CLK:3] [CLK_INV:0]
- RSTA=[RSTA:3] [RSTA_INV:0]
- RSTB=[RSTB:3] [RSTB_INV:0]
- RSTP=[RSTP_INV:0] [RSTP:3]
MULT18X18SIO_MULT18X18SIO
- AREG=[0:3]
- BREG=[0:3]
- B_INPUT=[DIRECT:3]
- CEA=[CEA_INV:0] [CEA:3]
- CEB=[CEB_INV:0] [CEB:3]
- CEP=[CEP:3] [CEP_INV:0]
- CLK=[CLK:3] [CLK_INV:0]
- PREG=[0:3]
- PREG_CLKINVERSION=[0:3]
- RSTA=[RSTA:3] [RSTA_INV:0]
- RSTB=[RSTB:3] [RSTB_INV:0]
- RSTP=[RSTP_INV:0] [RSTP:3]
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RAMB16
- CLKA=[CLKA_INV:0] [CLKA:11]
- CLKB=[CLKB_INV:0] [CLKB:11]
- ENA=[ENA_INV:0] [ENA:11]
- ENB=[ENB_INV:0] [ENB:11]
- SSRA=[SSRA_INV:0] [SSRA:11]
- SSRB=[SSRB_INV:0] [SSRB:11]
- WEA=[WEA:11] [WEA_INV:0]
- WEB=[WEB:11] [WEB_INV:0]
RAMB16_RAMB16A
- CLKA=[CLKA_INV:0] [CLKA:11]
- ENA=[ENA_INV:0] [ENA:11]
- PORTA_ATTR=[16384X1:3] [2048X9:8]
- SSRA=[SSRA_INV:0] [SSRA:11]
- WEA=[WEA:11] [WEA_INV:0]
- WRITEMODEA=[READ_FIRST:11]
RAMB16_RAMB16B
- CLKB=[CLKB_INV:0] [CLKB:11]
- ENB=[ENB_INV:0] [ENB:11]
- PORTB_ATTR=[16384X1:3] [2048X9:8]
- SSRB=[SSRB_INV:0] [SSRB:11]
- WEB=[WEB:11] [WEB_INV:0]
- WRITEMODEB=[READ_FIRST:11]
SLICEL
- BX=[BX_INV:18] [BX:204]
- BY=[BY:127] [BY_INV:10]
- CE=[CE:120] [CE_INV:0]
- CIN=[CIN_INV:0] [CIN:176]
- CLK=[CLK:285] [CLK_INV:0]
- SR=[SR:0] [SR_INV:277]
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SLICEL_CYMUXF
- 0=[0:212] [0_INV:0]
- 1=[1_INV:0] [1:212]
SLICEL_CYMUXG
SLICEL_F5MUX
SLICEL_F6MUX
SLICEL_FFX
- CE=[CE:95] [CE_INV:0]
- CK=[CK:244] [CK_INV:0]
- D=[D:243] [D_INV:1]
- FFX_INIT_ATTR=[INIT0:244]
- FFX_SR_ATTR=[SRLOW:244]
- LATCH_OR_FF=[FF:244]
- SR=[SR:0] [SR_INV:239]
- SYNC_ATTR=[ASYNC:244]
SLICEL_FFY
- CE=[CE:79] [CE_INV:0]
- CK=[CK:205] [CK_INV:0]
- D=[D:203] [D_INV:2]
- FFY_INIT_ATTR=[INIT0:203] [INIT1:2]
- FFY_SR_ATTR=[SRLOW:203] [SRHIGH:2]
- LATCH_OR_FF=[FF:205]
- SR=[SR:0] [SR_INV:197]
- SYNC_ATTR=[ASYNC:205]
SLICEL_XORF
SLICEM
- BX=[BX_INV:0] [BX:10]
- BY=[BY:12] [BY_INV:0]
- CE=[CE:5] [CE_INV:0]
- CLK=[CLK:7] [CLK_INV:0]
- SR=[SR:2] [SR_INV:5]
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SLICEM_F
SLICEM_F5MUX
SLICEM_F6MUX
SLICEM_FFY
- CE=[CE:5] [CE_INV:0]
- CK=[CK:7] [CK_INV:0]
- D=[D:7] [D_INV:0]
- FFY_INIT_ATTR=[INIT0:7]
- FFY_SR_ATTR=[SRLOW:7]
- LATCH_OR_FF=[FF:7]
- SR=[SR:0] [SR_INV:5]
- SYNC_ATTR=[ASYNC:7]
SLICEM_G
- DI=[DI:2] [DI_INV:0]
- G_ATTR=[SHIFT_REG:2]
- LUT_OR_MEM=[LUT:10] [RAM:2]
SLICEM_WSGEN
- CK=[CK:2] [CK_INV:0]
- SYNC_ATTR=[ASYNC:2]
- WE=[WE_INV:0] [WE:2]
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