vga_crt Project Status (08/07/2010 - 20:40:47)
Project File: vga_crt.ise Implementation State: Programming File Generated
Module Name: vga_crt
  • Errors:
No Errors
Target Device: xc3s250e-4vq100
  • Warnings:
74 Warnings
Product Version:ISE 11.3
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
0 (Setup: 0, Hold: 0) (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 456 4,896 9%  
Number of 4 input LUTs 1,213 4,896 24%  
Number of occupied Slices 795 2,448 32%  
    Number of Slices containing only related logic 795 795 100%  
    Number of Slices containing unrelated logic 0 795 0%  
Total Number of 4 input LUTs 1,361 4,896 27%  
    Number used as logic 1,211      
    Number used as a route-thru 148      
    Number used as Shift registers 2      
Number of bonded IOBs 42 66 63%  
Number of RAMB16s 11 12 91%  
Number of BUFGMUXs 1 24 4%  
Number of MULT18X18SIOs 3 12 25%  
Average Fanout of Non-Clock Nets 3.39      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent金 8 6 10:48:56 2010064 Warnings11 Infos
Translation ReportCurrent金 8 6 10:49:00 2010000
Map ReportCurrent金 8 6 10:49:05 2010010 Warnings1 Info
Place and Route ReportCurrent金 8 6 10:49:29 2010005 Infos
Power Report     
Post-PAR Static Timing ReportCurrent金 8 6 10:49:32 2010003 Infos
Bitgen ReportCurrent土 8 7 20:40:46 2010000
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of Date木 8 5 19:00:20 2010
Post-Synthesis Simulation Model ReportOut of Date木 8 5 17:59:45 2010

Date Generated: 08/07/2010 - 20:40:47