vga_crt Project Status (08/07/2010 - 20:40:47) | |||
Project File: | vga_crt.ise | Implementation State: | Programming File Generated |
Module Name: | vga_crt |
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No Errors |
Target Device: | xc3s250e-4vq100 |
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74 Warnings |
Product Version: | ISE 11.3 |
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All Signals Completely Routed |
Design Goal: | Balanced |
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All Constraints Met |
Design Strategy: | Xilinx Default (unlocked) |
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0 (Setup: 0, Hold: 0) (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 456 | 4,896 | 9% | ||
Number of 4 input LUTs | 1,213 | 4,896 | 24% | ||
Number of occupied Slices | 795 | 2,448 | 32% | ||
Number of Slices containing only related logic | 795 | 795 | 100% | ||
Number of Slices containing unrelated logic | 0 | 795 | 0% | ||
Total Number of 4 input LUTs | 1,361 | 4,896 | 27% | ||
Number used as logic | 1,211 | ||||
Number used as a route-thru | 148 | ||||
Number used as Shift registers | 2 | ||||
Number of bonded IOBs | 42 | 66 | 63% | ||
Number of RAMB16s | 11 | 12 | 91% | ||
Number of BUFGMUXs | 1 | 24 | 4% | ||
Number of MULT18X18SIOs | 3 | 12 | 25% | ||
Average Fanout of Non-Clock Nets | 3.39 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | 金 8 6 10:48:56 2010 | 0 | 64 Warnings | 11 Infos | |
Translation Report | Current | 金 8 6 10:49:00 2010 | 0 | 0 | 0 | |
Map Report | Current | 金 8 6 10:49:05 2010 | 0 | 10 Warnings | 1 Info | |
Place and Route Report | Current | 金 8 6 10:49:29 2010 | 0 | 0 | 5 Infos | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | 金 8 6 10:49:32 2010 | 0 | 0 | 3 Infos | |
Bitgen Report | Current | 土 8 7 20:40:46 2010 | 0 | 0 | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | 木 8 5 19:00:20 2010 | |
Post-Synthesis Simulation Model Report | Out of Date | 木 8 5 17:59:45 2010 |