s3e_led Project Status (08/09/2010 - 18:34:32) | |||
Project File: | s3e_led.ise | Implementation State: | Programming File Generated |
Module Name: | s3e_led |
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No Errors |
Target Device: | xc3s250e-4vq100 |
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No Warnings |
Product Version: | ISE 11.3 |
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All Signals Completely Routed |
Design Goal: | Balanced |
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All Constraints Met |
Design Strategy: | Xilinx Default (unlocked) |
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0 (Setup: 0, Hold: 0) (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 27 | 4,896 | 1% | ||
Number of 4 input LUTs | 34 | 4,896 | 1% | ||
Number of occupied Slices | 31 | 2,448 | 1% | ||
Number of Slices containing only related logic | 31 | 31 | 100% | ||
Number of Slices containing unrelated logic | 0 | 31 | 0% | ||
Total Number of 4 input LUTs | 59 | 4,896 | 1% | ||
Number used as logic | 34 | ||||
Number used as a route-thru | 25 | ||||
Number of bonded IOBs | 3 | 66 | 4% | ||
Number of BUFGMUXs | 1 | 24 | 4% | ||
Average Fanout of Non-Clock Nets | 2.13 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | 月 8 9 18:34:12 2010 | 0 | 0 | 0 | |
Translation Report | Current | 月 8 9 18:34:15 2010 | 0 | 0 | 0 | |
Map Report | Current | 月 8 9 18:34:19 2010 | 0 | 0 | 2 Infos | |
Place and Route Report | Current | 月 8 9 18:34:25 2010 | 0 | 0 | 4 Infos | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | 月 8 9 18:34:27 2010 | 0 | 0 | 3 Infos | |
Bitgen Report | Current | 月 8 9 18:34:31 2010 | 0 | 0 | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | 土 8 7 04:14:55 2010 |