s3e_led Project Status (08/09/2010 - 18:34:32)
Project File: s3e_led.ise Implementation State: Programming File Generated
Module Name: s3e_led
  • Errors:
No Errors
Target Device: xc3s250e-4vq100
  • Warnings:
No Warnings
Product Version:ISE 11.3
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
0 (Setup: 0, Hold: 0) (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 27 4,896 1%  
Number of 4 input LUTs 34 4,896 1%  
Number of occupied Slices 31 2,448 1%  
    Number of Slices containing only related logic 31 31 100%  
    Number of Slices containing unrelated logic 0 31 0%  
Total Number of 4 input LUTs 59 4,896 1%  
    Number used as logic 34      
    Number used as a route-thru 25      
Number of bonded IOBs 3 66 4%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 2.13      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent月 8 9 18:34:12 2010000
Translation ReportCurrent月 8 9 18:34:15 2010000
Map ReportCurrent月 8 9 18:34:19 2010002 Infos
Place and Route ReportCurrent月 8 9 18:34:25 2010004 Infos
Power Report     
Post-PAR Static Timing ReportCurrent月 8 9 18:34:27 2010003 Infos
Bitgen ReportCurrent月 8 9 18:34:31 2010000
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of Date土 8 7 04:14:55 2010

Date Generated: 08/09/2010 - 18:34:32